Example: FinFET geometry: fins with height ~40–60 nm and fin pitch scaled to control effective channel width; multiple fins used to achieve required drive current.
Van Zant does not shy away from the business reality. A modern fab costs $10–20 billion. The equipment (EUV scanners from ASML costing $200 million each) is obsolete within 5 years. The essay concludes by analyzing the limits Van Zant foresaw: the (gates at 3nm are only 15 silicon atoms wide), quantum tunneling (leakage current), and the end of Dennard scaling (transistors no longer get faster as they shrink due to power density). microchip fabrication peter van zant pdf
You might ask: “Van Zant’s book covers older nodes. Does it matter?” Absolutely. The physics of the 5nm and 3nm processes are proprietary secrets of TSMC, Intel, and Samsung. However, the fundamentals Van Zant teaches—how a stepper works, why you need chemical mechanical planarization, how to calculate die yield—have not changed. You cannot understand a GAAFET (Gate-All-Around FET) if you don’t understand the basic MOSFET process Van Zant explains first. Example: FinFET geometry: fins with height ~40–60 nm